Device for decoding pulse-coded data

ABSTRACT

A decoder device for decoding binary codes words each formed by a sequence of (n-1) logic conditions at a clock period theta . The code words are contained within a pair of &#39;&#39;&#39;&#39;frame&#39;&#39;&#39;&#39; pulses. A high clock frequency is used with a unique arrangement of timing circuits minimizes the number of shift register stages required in the decoding circuitry. The circuits allow for pulse time position tolerances of + OR - Delta theta and a corresponding unity recognition probability band between theta + Delta theta and theta - Delta theta .

United States Patent 1191 1111 3,913,100 Janex Oct. 14, 1975 DEVICE FOR DECODING PULSE-CODED DATA Primary Examiner-Malcolm F. Hubler [75] Inventor: Albert Janex, Cachan, France Attorney, Agent, or FirmWilliam T. ONeil [73] Assignee: International Standard Electric Corporation, New York, NY.

22 Filed: Dec. 20, 1973 [57] ABSTRACT [211 App! 426528 A decoder device for decoding binary codes words each formed by a sequence of (n-l) logic conditions [30] Foreign Application Priority Data at a clock period 0. The code words are contained Feb. 22, 1972 France 72.45920 Within a P of pulses- A high clock quency is used with a unique arrangement of timing [52] US Cl. 343/65 328/119; 329/107; circuits minimizes the number of shift register stages 343/68 LC required in the decoding circuitry. The circuits allow 51 Int. 01. G018 9/56; H03K 9/04 for Pulse time Position tolerances of 1 A6 and a Corre- [58] Field of Search 343/5 DP, 68 LC, 65 LC; sponding unity recognition probability band between 6 [56] References Cited UNITED STATES PATENTS 3,721,906 3/1973 Geesen et al. 343/68 LC X A6 and 6 A0.

9 Claims, 1 Drawing Figure 123 As: 7/02/17 9 O el/i2 f1 DEVICE FOR DECODING IULSE-CODED DATA BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to decoder devices for decoding data or encoded words arranged in the form of combinations of regularly spaced pulses.

2. Description of the Prior Art Secondary radar systems wherein encoded words or codes are transmitted by an airborne transponder in response to encoded interrogations transmitted by a ground station constitute an example of a system in which the present invention is particularly useful.

The state of the coded-reply transponder art is described in the technical literature. Chapter 38 of the text Radar Handbook" by Merrill Skolnik (McGraw Hill 1970) is useful in providing a background in this art. US. Pat. No. 2,741 ,759 is also of interest in understanding the general class of devices to which the present invention may be applied.

In general, each encoded word includes a sequence of (nl logic conditions or 1, the 1 being represented by a pulse edge-spaced by time intervals of standard value 6. Those sequences of conditions permit the generation of 2" binary codes, each code including (nl bits.

ln known prior art, replies are decoded by means of a shift register fed by a clock having a period (or step) which is a submultiple (19/g) of 6 (g being an integer).

Time interval between logic conditions of a code is determined to a predetermined tolerance A6 with respect to the standard value 6.

Since any word comprising successive logic conditions spaced by an out-of-tolerance time interval must be rejected during the decoding operation, a clock step (G/g) (g being an integer) must be selected which is at the longest equal to A6; that is g z (6/A6). In such conditions, taking into account the fact that shift register operation has a quantized character, the probability of the decoder to accepting two successive pulses, which is unity when the time interval is equal to standard value 6, decreases linearly to 0 when the time interval varies from 0 to i (O/g).

In order to broaden the decoding operation conditions, which may be accepted as far as interval tolerances are concerned, certain rather sophisticated artifices have been adopted in the prior art to permit an operating range wherein recognition probability is equal to 1 for deviations from standard value between 0 and i (11/2) (O/g), bracketed by two areas wherein recognition probability linearly decreases from 1 to O whendeviation varies from (11/2) (6/g) to and from (11/2) (6/g) to In such conditions, the complete deviation area for recognizable deviations is and there is need for (h 2) (ti/g) 2 A6, that is Considering a word with standard time interval of 0 1.45 #5, with A6 0.2 ps, and assuming that h 0, the value of g is 8.

It will be then necessary for decoding a word comprising only two pulses spaced by 1.45 ,us to utilize an eight-stage shift register with a clock step of O. 18 1.15. As messages utilized in secondary radar system may comprise up to 14 successive conditions with standard spacing of 1.45 pm (tolerance remaining the same for any pair of adjacent pulses) it appears-that the shaft register must comprise l 12 stages.

If it is attempted to improve decoding conditions by taking h 3, the following values are respectively found: (0/g) s ns, g= 19.

Thus, now 19 stages are needed for decoding a word limited to two pulses spaced by 1.45 1.9, and 266 stages are needed for decoding a message comprising 14 successive conditions.

The need to make a fine analysis of the decoded message and to have a good probability of recognizing acceptable pulses, as far as time interval tolerances are concerned, thus requires large shift register capacity.

Moreover, it is to be noted that the quantized operation character of the shift register results in a precise relation between tolerance and clockstep (B/g), i.e.,:

(with h=O, 1, 2,...)

The manner in which the present invention improves upon the foregoing state of the art will be understood as this description proceeds.

SUMMARY One of the purposes of the present invention is to provide a decoder device capable of decoding 2(n1) encoded words, arranged in the form of combinations of O to (n-l) pulses plus an initial (reference) pulse, wherein the register utilized has a number of stages equal to n.

The device according to the invention is usable when the word to be decoded is free from any interference signal (noise or jamming). Such a device finds its best application in test apparatus for secondary radar responder systems.

According to this invention, the word decoding operation is performed by means of a shift register fed by a clock having a step equal to a standard time interval 0 between logic conditions of the word to be decoded.

The device according to this invention makes it possible to decode words wherein pulses are located at their standard position with a tolerance of A6, with that tolerance substantially independent of the clock step 0. The deviation areas on each side of the standard interval 6, wherein the probability of pulse recognition varies from to l, are reduced and independent of the clock step. The probability of accepting or recognizing time intervals between 6 A6 and 6+ A6 thus is substantially equal to l.

The decoder device according to this invention is associated with a number of well-known conventional circuit, including high frequency circuits which receive signal modulated by an encoded word, detection circuits for encoded word recognition, and circuits for shaping encoded word pulses.

In the following, only leading edges of reshaped pulses will be considered as operating the decoder device input.

According to a feature of this invention, reshaped pulses trigger a first timing circuit, such as a monostable circuit having a switching duration or time constant 2 A6. Each so generated pulse, having a width 2 A6, is applied to the input of a shift register, which may be controlled by a clock having a period 6 and comprising a synchronous divider-by-k receiving pulses, at frequency (It/6), from a highly stabilized generator. The leading or initial pulse, which always exists in a word, also triggers a second timing circuit, having a time constant A6, which controls, at the end of that time A6, the operation of the divider-by-k and thus of the clock for a time T determined by a timing circuit having a time constant T (T being substantially longer than the duration of the longest word to be decoded).

A pulse, having width 2 A6, corresponding to the reference pulse enters the first stage of the shift register as soon as divider-by-k is turned on, and is thus in the middle of time interval 26. It is this divider-by-k turning-on time which serves, as a reference, for processing the following pulses of the word to be decoded.

Each of the successive reshaped pulses triggers, in turn, the first timing circuit, having a time constant 2 A6, and either enters or is rejected by the shift register at the rate of clock step 6, depending on the time interval from the reference pulse [if inside or outside of (56 i A6) In that relation, s indicates the pulse rank of the pulse in the word to be decoded [l s s (11-1)].

It may still be that the clock is synchronized on the reference pulse leading edge delayed by A6, the synchronization being made with a statistic uncertainty equal to (6/2k), i.e. half period of the highly stabilized generator.

Thus it appears that areas where the probability of receiving encoded word pulses in the shift register varies from O to l, are limited to two fringes of width (6/2k), located on the borders of tolerance time intervals A6 to A6.

Thus, practically, it is sufficient to select k such as (6/2k) 1 A6.

According to a well-known process, encoded word pulses, after having been accepted, are shifted by one stage, in the shift register, for each clock pulse. According to this invention, when the reference pulse has reached a predetermined stage in the said register, outputs conditions of the following stages represent, in parallel, the conditions 0 or 1 corresponding to a binary word, which is the encoded word to a higher order of certainty, if time interval between each pulse and the reference pulse is within tolerances i A6.

According to known processes, the binary word from register outputs is normally decoded and stored, and the shift register is reset, so as to receive the next word to be decoded.

Replies from secondary radar transponders usually are bracketed by two frame pulses F and F which always exist spaced by [(n+l) 6 i A6] enclosing from O to 11 pulses, which may constitute 2" binary codes with (nl bits (they are the normal replies to interrogations) and m special codes, called code X.

It is to be noted that normal replies are different from the encoded word considered up to now, by the addition of an end pulse F and a condition representing a special code X.

In certain cases, transponders may transmit, after a normal reply, special messages comprising either a pulse, called SPl, spaced from F by (m6 i A6), or 1 words comprising, at least, two frame pulses F, and F spaced by [(n+l) 6 A6], time intervals from F and F as well as F and F being (m6: A6). A normal reply followed by a pulse SPl may constitute a position identification code. Followed by q words, a special message or code characterized by the number (q-H) (mayday message, for example) is constituted.

A decoder device having the above mentioned feature can be, with a few adaptations, utilized for decoding special codes.

First it is to be noted that, in the described device,

the reference pulse is the first frame pulse F, of a normal reply, and

for each time interval (m6 1': A6) or [(n+l )6 i A6],

the new reference for acceptance or rejection of a pulse which follows the normal code is not the pulse F, which terms the divider after a time 6, but pulse F SP1 or F F etc. up to F The timing circuit, having time constant T is slightly longer than the longest special code length.

According to a feature of the decoder device, arranged according to this invention, the shift register comprises (lz+2+m) stages, the outputs of the 2nd and 3rd. (.r-l )th, (x+l )th (n+1 )th stages being connected to inputs of a first decoder. A specific output of the xth stage is connected to the input of a second decoder alloted to recognition of special codeX.

A first three-input coincidence circuit, having one inhibition input, which may be on, only for time T slightly long than [(n+l 6+ 2 A6], and determined by a timing circuit having a time constant T is turned on when pulses F and F respectively enter the (n+2)th and lst stages of the shift register. The on-condition of the said first coincidence circuit causes the binary word delivered from the shift register output, after decoding, at the coincidence time, to be stored.

A second four-input coincidence circuit, having one inhibition input, which may be turned on only at the end of a time T slightly longer than [(nll+m)6 2 A6], and determined by a timing circuit having a time constant T is actually turned on after time T when F F, and F respectively enter the (n+2+m )th, (n+2)th and lst shift register stages. Then, it is turned on when F F and F respectively enter the same stages and so on up to F F, and F A counter of capacity (q-l-l counts the number of on-conditions for the second coincidence circuit and this number characterizes a special code.

Another feature of the decoder device presented permits successive synchronization of the clock, at step 6, on leading edges of pulses F SPl or F F Ff, Ff delayed by A6. According to this feature, the leading edge of each pulse of width 2 A6, generated by the timing circuit having a time constant 2 A6, controls the triggering of a timing circuit having a time constant 0. Simultaneously, the same leading edge, if a pulse F SPI, F,, F F, has been recognized by the shiftregister, causes, for a time 0, by means of an assembly of logic gates, the generation of a signal which allows the third coincidence circuit to be turned on. This actually occurs at the end of the time defined by the timing circuit having the constant time 0. The turning on of the third coincidence circuit triggers a second timing circuit having atime constant A0 which controls, for the time A0, the operation of divider-by-k. At the end of time A0, the clock, at step 0, is synchronized by one of the pulses and F," to (0/2k).

Thus, it appears in the new synchronization process, the timing circuit, having time constant 0, temporarily replaces the clock, at step 0, and that the second timing circuit, having time constant A0, has the same function with respect to pulses F to F, as the first timing circuit having the same time constant A0 with respect to the first frame pulse F,".

When the device according to this invention is used in a secondary radar responder test apparatus, one must ascertain that pulse F," appear, at the device input, after a certain time lying between T, and T2 following the transmission from the interrogator of reference pulse, called P According to another feature of this invention, two cascaded timing circuits, having respectively time constants T, and (T2 7,), controlled by pulse P allow the clock, at step 0, to be switched on via the first timing circuit having time constant 2 0 and the second timing circuit having time constant A0, only within a time interval from 1', to r after the transmission of P Other features of this invention will appear more clearly from the following description of an embodiment, the said description being made in conjunction with the accompanying drawing. The device is particu larly useful for testing for correct transponder encoder and transmitting functions.

BRIEF DESCRIPTION OF THE DRAWINGS A single FIGURE presents a functional and logical diagram of the circuits of an embodiment of the invention, with particular reference to a decoder for coded transponder replies.

DESCRIPTION OF THE PREFERRED EMBODIMENT In a secondary radar system, the ground station interrogator transmits trains of at least two pulses, the time interval between extreme pulses (P, and P characterizing an interrogation mode. In known systems, if airborne equipment is capable of recognizing an interrogation mode, it transmits a first pulse F, at time 1',, i A'r t, after the transmission of pulse P by the interrogator. That pulse F, will be received in the ground station, at time 1,, 1 A7,, 2z,.

1,, corresponds to internal transponder delay, i A7,, corresponds to internal delay tolerance, and 2t, measures round trip transmission time of RS signals comprising interrogation and encoded reply.

In most airborne equipments, 1,, 3 ps and A7,, 0.5

Following the first frame pulse F, and at regular intervals 0. the transponder transmits 11 conditions 1 or 0 corresponding to the presence or absence of a pulse leading edge. The sequence of (11-1) of those conditions determines an encoded reply word or code out of the 2" possible codes. The nth condition is available to provide, for example, a specific feature information X, which may be of interest at the ground station.

At time 0, after having generated the nth condition of its reply, the transponder delivers a second frame pulse F The time interval between leading edges of F and F is equal to (n+1) 0, and for that time interval, a tolerance equal to i A0. i A0 also determines the tolerance on the time interval between F, and each of the code pulses.

In known equipments, 11 13, 0 1.45 as and A0 0.2 .45. The interval (F F,) then is of the order of (20.3 i 0.2) ps.

The number of possible codes is equal to 2 or 4096. Besides those 2" replies normal codes and information X, the transponder may provide, at the ground operators request, a specific code, called position identi fication,

either, in the form ofa pulse SPI delivered at time m0 i A0 following pulse F (case of interrogation modes called 2, 3 and c),

or, in the form of a repetition of the first reply word, pulse F, of the repetition occurring at time (1210 i A0) after pulse F of the first word (case of interrogation mode called 1).

Finally, in mayday cases, the interrogated transponder may reply to an interrogation with a third reply word such as it has been hereabove defined, followed at time intervals (m0 1 A0) by q empty words (that is limited to only frame pulses F and F spaced by (n+1) 0 i A0). The length of a specific message or mayday code is thus equal to:

Practically, n 3 and q 3 with m 13; A0 0.2 pa; 0 1.45 ,us.

The normal length of a mayday message is thus 65 0 94.25 #5 with an uncertainty of i: 7 A0 i 1.4 as.

Either normal or specific codes are transmitted in sequence at time intervals t, of about 2.5 ms (repetition frequency (l/z,.) is about 400 Hz).

From the above it appears that the device, shown in FIG. 1, must comprise a number of timing circuit which determine the time durations to be taken into account for allowing the decoder to accept or reject encoded pulses or words. Those circuits are constituted by monostable circuits having free-running periods or time constants equal to:

2 A 0 0.4 ,us

T, is slightly longer than [(n-H) (q-l-l mq] 0 (2q 1) A0, (that is, in this case, slightly longer than 96 n).

T is slightly longer than (n+1) 0 2 A0 2 Ar (that is, in this case, slightly longer than 21.7 ,us),

and T is slightly longer than [(n+1) m] 0 2 A0,

(that is, in this case, slightly longer than 25 as). Referring now to FIG. 1, several types of logic circuits such as flip-flops, monostable circuits and gates will be recognized.

As a rule, flip-flops turn their condition when a leading pulse edge is applied to their pulse input 11 (switching from O to l).

In the diagram, each flip-flop also has a priority input C and, possibly, another priority input S. When level is applied to input C, output Q of the flip-flop is turned to condition 0. On the contrary, level 0 applied to input S causes output Q to turn to condition 1.

Output Q of each monostable circuit in the drawing is turned from condition 0 to condition 1 by applying to its input a leading edge, and turns back to initial 0, after a time t (t,, self-timing period or time constant). Such a time t is well determined after that the said leading edge has been applied.

In the drawing, a monostable circuit called retriggerable circuit" is also used. In such a monostable circuit, if a second leading edge is applied to the input, at a time t after the first leading edge, the output holds condition 1 during a time 1,, t.

For language convenience, logic gates in the FIG. 1, will be considered as off when their output is in condition 0, and on in the reverse case.

In the description, F, and F will indicate frame pulses for a normal code, when they enter the device and F F F F will indicate frame pulses of following words, in case of decoding a specific code.

The diagram comprises three blocks 1, I1 and III. Block I basically comprises circuits for encoding and transmitting interrogations according to several predetermined modes,

circuits for receiving, detection and reshaping reply pulses from a transponder replying to recognized interrogations, and

an assembly of monostable circuits which generate the various timing durations, as hereabove mentioned, Block 11 basically comprises circuits for recognizing and decoding normal codes. Block 111 basically comprises circuits for recognizing and decoding specific codes.

Description of Block 1:

Box 1 is an interrogation signal generator which delivers the signal needed for triggering the responder on one or several modes.

Box 2 is a modulator which converts the interrogation signal delivered from 1 into RS frequency.

Box 3 is the RF signal transmitter for transmitting signals from 2.

An antenna 4, provided with a circulator, radiates toward the transponder, not shown, the signals from 3, and receives from the transponder encoded replies carried by the RS signal.

A receiver 5 delivers from its output the detected signal in the form of a train of reshaped pulses which reproduce the reply, as encoded in the transponder.

An assembly of test circuits 6 permits testing transponder characteristics particularly as far as radiated power and RS frequency are concerned.

In the transponder test equipment, antenna 4 may be replaced by a coaxial cable provided with a directional coupler which connects the output of 3 to the transponder under test. Whatever the adopted connection mode, round trip time for messages at RS frequency, is

well defined and is equal to 2t,. Here it will be assumed that 22 0.2 ps.

One output of 1, from which only pulse P of interrogations is delivered, is connected to an input of a monostable 7 having a free-running duration of 1' 1,, A7,, 2t, (that is here 2.7 ps).

Output Q of 7 is connected to an input of monostable circuit 8 having free-running (self-timing) duration of 2A'r r 1', (that is here 1 ,us).

Output Q of 8 is connected to data input D of a flipflop 9. Output Q of 9 is connected to one end of a resistor 10a having its other end connected to one plate of a capacitor 10b having its other plate grounded; 10a and 10b forming a delay circuit 10 having a delay time equal to A0 (ie 0.2 as). Box 10 represents the first timing circuit having a time constant A0, as mentioned hereinbefore.

The output of receiver 5 is connected to an input of monostable circuit 11 having a free-running duration of 2 A0 (i.e. 0.4 #5).

Output Q of 11 is connected to pulse input h of flipfiop 9, via a connection 12 and branch 12a thereof.

Line 12 also connects block I to block 11.

A connection is established between common junction point of 10a and 10b, and the input of monostable 13 having a free-running duration which is slightly longer than [(n+l) (q-H) mg] 0 i (2q-1-l) A6, i.e., longer than 96 ps. T is for example selected equal to ps. I

Output Q of 13 is connected to one of a two-input AND gate 16 whose other input is connected, via line 15 to output Q of a monostable circuit 14 having a freerunning duration A6.

Gate 16 usgally is off and is turned on only if outputs Q of 13 and Q of 14 are simultaneously in condition 1.

Line 27 from output of AND gate 16 enters block 11, operation of which is allowed only if gate 16 is on.

A branch 12b of line 12 is connected to input of a retriggerable monostable circuit 17, having a freerunning duration equal to 6. Output Q of 17 is connected, via line 18, to one of a two-input AND gate 19 having its other input connected, via line 39, into block 111. The output of 19 is connected, via line 20, to input of monostable circuit 14. Circuit 19 represents the third coincidence circuit mentioned hereinbefore.

Usually, gate 19 is off and output Q of 14 is at level 1. In such conditions, the on or off condition of gate 16 depends only on condition 1 or 0 of output Q of 13.

It will be seen that gate 19 and monostable circuit are not involved in the decoding operation of specii mayday or position identification codes.

A line 22 is established from output Q of 8 to block 111.

Similarly, line 24 is established from output Q of 8 to block 111.

The input of monostable circuit 21 is connected from output Q of 7 while output Q of 21 is connected, via line 26, to block II.

The free-running duration T of 21 is slightly longer than [(n+l 0 2A6 2A T that is, in the described embodiment longer than 21.7 as. For example, T is selected equal to 22 ps.

Monostable circuit 21 prevents decoding (in block II) of pulses which would be outside of interval F F defined by the frame pulses of a normal word.

The input of monostable circuit 23 is conn ected, via

' line 12-12C, from output Q of 11. Output Q of 23 is connected, via line 25, tocircuits of block Ill. The freerunning duration T of 23 is likely longer than [(n+l) m] 6 2A6, that here longer than' 25 us. For example, T is selected equal to 26 [1.8. Monostable circuit 23 prevents counting, in block III, of the first interval F F, recognized in block II.

Operation of Block I:

When an interrogation pulse P is generated by 1, after a time duration normally between 2.7 ps and 3.7 Us, the frame pulse F of the reply transmitted from the transponder is delivered from output of 5 to switch 11, whose output Q is the turned to condition I and is also delivered as input h of flip-flop 9.

If the change condition of input h of 9 occurs within a time comprised between 2.7 ,us and 3.7 4s after transmission of P flip-flop 9 is switched and output Q of 9 has the value 1, corresponding to the condition of its input D. Capacitor 10b of circuit 10 is charged in a time A6= 0.2 ,us. At the end of that time, 13 is switched and output Q of 13 goes to condition 1 for a time T equal to I [.08. AND gate 16 is turned on and via line 27, and block ll is allowed, provided that certain conditions are met, to decode the reply word following the frame pulse F If F, is delivered from output of outside the aforesaid limits (2.7 .4.s to 3.7 ,us), after the generation of P by 1, it is not recognized as the first frame pulse of a possible reply since there is no condition change in 9 and, therefore, gate 16 remains off.

Considering timing circuits 10, 11 and 13, it is now understood that the occurrence of the leading edge of the first frame pulse F, constitutes the reference for measuring time elapsed from the first frame pulse F to a pulse of rank s in a normal reply word. If, as it will further appear, the time is outside interval s6 i A6, pulse of rank s is not considered in the decoder of block The same is obviously true for theframe pulse F at the end of a word, i.e., it will not be considered if it appears at a time outside of interval (n+1 )6 :t A6. Description of block lI:

' High frequency oscillator 28 delivers pulses of period (6/k) which are substantially shorter than A6.

If, for example,

vider-by-k 29.

All flip-flops in a chain which constitutes divider 29, are provided with a priority reset input C and divider 29 does not operate as long as input C is maintained in condition 0 by line 27. The output of 29 is connected to clock input h of shift register 30, the latter including (n+2+nz) stages (that is, here 18) referenced from S to S 1 f i The twelve outputsof stagesS S and S S are associated with decoder 3l wherein, during operation of register 30, binary numbers, each having 12 bits determined by either condition l-or O of outputs S S and S S are written in decimal code, at the rate6.

The output of 31 is connected to the input of memory 33 which is provided with a writing enable input C. When a level() is applied to C, memory 33 stores the number which is, at that time, isi registered in 3 1, that number also appearing on a display 35. i

In a same manner the output of stage 5,, of register 30 is connected to the input of memory 32, provided with writing enable input C. When level 0 is applied to C, memory 32 stores the binary data (data X), registered at that time on output of S such data also appearing on a display 34. A three-input NAND gate 36 has its first input connected, via line 26, from output Q of monostable circuit 21 (block I); its second input connected, via line 41 and its branch 41a, from the output of stage S of register 30; and its third input connected, via line 42 and its branch 42a, from output of stage S of 30. The first coincidence circuit NAND gate 36, as hereinbefore indicated, is substantially always open and is only closed when the three inputs of NAND gate 36 are simultaneously at level 1.

The output of 36 is connected, via line 38 and its branch 38a, to writing enable inputs C of memories 32 and 33. A branch 38b of 38 enters block III.

Operation of block II in association with block I:

When pulse F occurs from the output of 5, within the time limits determined by monostable circuits 7 and 8, it turns the condition of outputs Q of 11 and of 9, then, after a time A6 via 10 also the condition Q of 13. Gate 16 is turned on, the output of divider 29 is turned to level 1 and the first clock pulse, at rate 6 (i.e. 1.45 ps), controls register 30. That first clock pulse, at rate 6, is generated after a time comprised between 0 and (6/k), after 16 has turned on.

Via line 12, level 1 from output Q of 11 has been applied to the input of register 30, at a time preceeding the first clock pulse by A6. When that first clock pulse occurs, level 1, corresponding to the leading edge of pulse F turns the output of stage S of 30 to I.

At each pulse of rank s of a normal reply word, occurring within a time period comprised between (s6 A6) and ($6 A6) after F 11 is switched on during a time 2A6 (i.e.: 0.4 ps) and level 1, corresponding to the leading edge of that pulse of rank s, is applied to input of 30. After a time, at most 2A6, the (s+l)th clock pulse, at a rate 6, which controls 30, causes the output of stage S of 30 to be turned to condition 1. At that time, pulse F which has already been shifted by s stages in 30, turns the output of the (s+l )th stage.

Thus all the pulses of a normal word are shifted, in register 30, from left to right, at rate 6.

Such a shift is continued up to the occurrence (from 5) at the end of a normal reply word, of the second fram pulse F If it occurs within the correct time limits [between (n+1 )6 A6 and (n+1 )6 A6, i.e. between 20.1 ps to 20.5 us]; it enters, in turn, register 30 under the control of the next clock pulse at rate 6.

At that time, the condition of register 30 is as follows:

output of stage S containing pulse F is at level 1;

outputs of stages S S and S S correspond to a binary coded word having 12 bits, which reproduces the normal reply if each pulse in that reply is correctly spaced from F, by $6 i A6:

output of S delivers data X;

output of 8,, containing pulse F is in condition 1.

As soon as F has entered, a decimal coded number is delivered from the output of decoder 31, such a number corresponding to the binary coded reply appearing on the outputs of stages S S and S S of register 30.

As soon as F, and F have respectively entered stages S 5 and the three inputs of NAND gate 36 are all at level 1. Gate 36 is off, which means that it has recognized a reply which may be accepted as far as the time interval from F to F is concerned.

Writing enable input C of memories 32 and 33 are in condition 0. The word, decoded in 31, is stored in memory 33 while data X enters membory 32. Displays 35 and 34 respectively display the normal reply code number and data X, gathered on the run" by memories 33 and 32.

It should noted that, if the time interval from F to F is out oflimits, the reply word is not displayed since gate 36 is not off and, during time T (i.e.: I [4.8), clock pulses, at rate 6, shift rightwards the conditions registered on outputs of register 30 which is progressively emptied. At the end of time T all the circuits, in blocks I and II, are reset to their initial conditions and are ready to process the next normal reply. If the time interval from F," to any pulse of the processed word is not within the limits s0 i At), the decoded word, displayed in 35, is different of the coded word from the transponder. That fact is of significance in when the device is employed for evaluating the operation of the transponder encoder. Indeed, it is easy to compare the displayed replies in 34 and 35 with those encoded by the transponder.

Description of block III:

In block III, a two-input NAND gate 37 has one of its inputs connected from the output of stage 5, of register 30, via line 41 and its branch 41b, and the other input connected from the output of stage S of register 30 (block ll), via line 43.

The output of 37 is connected to one input of a twoinput NAND gate 40.

Via a branch 38b of line 38, the other input of 40 is connected from the output of NAND gate 36 (block II).

The output of 40 is connected, via line 39, to one input of the two-input AND gate 19 of block I.

Gates 37 and 40 together constitute the logic gates aforementioned,

Gate 37 is almost always on and is turned off only in when its two inputs are at level 1. Accordingly, 40 is the most often off and is turned on only when one of the two gates 36 or 37 is in the off-condition.

AND gate 19, in block I, thus can be in the on condition only when one of the two gates 36 or 37 is off and output Q of 17 (block I) is at level 1.

It is to be noted that 36 is turned on after recognition of a normal code, since the third input of 36 is reset to level at the end of a time T slightly longer than [(n+l) 9 2A6]. As a result, for processing specific codes, only gate 37 is involved.

Considering in advance what will be further described, the arrangement of gates 36 (block II), 37- 40(block III) and 19 (block I) makes it possible to substitute, in certain cases, the time reference provided from monostable circuit 17 for the reference time resulting from occurrence of a pulse F, from output of (block I).

When 36 is turned on after time T it presents words bounded by F and F F and F etc., following a normal code written into memories 33 and 32.

A four-input AND gate 44 has its four inputs connected as follows:

The first input is connected, via branch 410 of line 41, from the output of stage S of register 30.

The second input is connected, via line 42 and its branch 42]), from output of stage S The third input is connected, via branch 43a of line 43, from the output of stage S Finally, the fourth input, which is an inhibition input, is connected, via line 25, from output of monostable circuit 23 (block I).

The output of44 is connected to an input of flip-flop 45 which, coupled to flip-flop 46, constitutes an asynchronous counter having a capacity (q-l-l (i.e. 4).

Outputs Q of 45 and 6 of 46 are respectively connected to the two inputs of AND gate 47. The output of 47 is connected to one of the terminals of a luminous indicator 48 having its other terminal connected ground (level 0). Luminous indicator 48 is operative when the output of 47 is at level 1. Indicator 48 is used in decoding and recognition of mayday signals. Indicator 48 has a time constant long enough to make it Operate as an integrator of successive conditions 1 from output of 47.

Output Q of 45 is connected to one input of a twoinput NOR gate 49 having its other input connected, via line 22, from output Q of monostable circuit 8 (block I). The output of 49 is connected to reset input C of flip-flop 50. The input S for setting 50 to l is connected, via line 53, from the output of gate 37.

The output Q of 50 is connected to one of the two contacts of a two-position switch 51. The other contact of 51 is connected from output Q of 46.

The prolonged presence of level I applied to the upper Contact enables luminous indicator 52 to decode specific position identification messages for interrogation mode 1. The prolonged presence of level I on the lower contact makes it possible to decode specific position identification messages via pulse SPI for the other interrogation modes.

Indicator 52 has a time constant long enough to allow it to operate as an integrator indicating prolonged conditions l of outputs Q of 46 and 50, but it does not recognize short duration condition changes which occur on the same output during specific mayday codes processing.

Operation of block III associated with blocks I and II:

Initially, after the generation of interrogation pulse P in 1 (block I), monostable circuit 7 is on for a time T monostable circuit 8 is, in turn, turned on, with its output 6 turned to level 0, such a level being transmitted, via line 24, to reset inputs C of flip-flops 45 and 46, causing the outputs Q to be turned to level 0. Similarly, output Q of 8 is turned to level 1, such a level being, via line 22, applied to one input of the two-input NOR gate 49, which is turned off, which turns output Q of 50 to O for the time period 1' 1' Gates 36 and 37 are on. Gates 19, 40 44 and 47 are off.

The process of shifting reply pulses through register 30 is first effected as hereabove mentioned.

When pulses F and F have respectively reached stages S 5 and S gate 36 is turned off while gate 40 is turned on. In turn, gate 19 is turned on as soon as monostable circuit 17 (which has been turned on when pulse F is applied to input register 30) has been reset after a time 0. In that case, monostable circuit 14 is turned on for a time A6, gate 16 is turned off and divider 29 is inoperative up to the reset of 14. The clock operating at rate 0 and consisting of elements 28 and 29, is again operated and is thus synchronized from pulse F but no longer from pulse Ff.

It will be noted that, with this new synchronization, monostable 14 operates as the delay circuit used in initial synchronization on F,".

Accordingly, the circuit is then prepared for decoding specific position identification or mayday messages, if any.

For the three possible specific messages, pulse SP1 (or pulse F, of another word bounded by pulses F, and F enters stage S, of register 30 at a time between (m6 A6) and m6 A6), (i.e. 4.15 as and 4.55 as), following pulse F At that time the outputs of stages S,and S,,, of 30 are at level 1 since F," has reached S Gate 37 is turned off, gate 40 is turned on is gate 19, if monostable circuit 17 has been reset. The new synchronization of the clock (consisting of 28 and 29) from pulse SPl or F,, is then effected as hereabove described.

When switch 51 is in the down position all illustrated, corresponding to the setting for recognition of a code SPI, luminous indicator 52 is operative due to the switching of flip-flop 50 controlled by the off-condition of gate 37.

If the decoded message is a specific code with position identification pulse SPl, output Q of 50 remains in condition 1 up to the occurrence, in 5 (block I), of the pulse F, of the next word, i.e. for about a time t, pf ms for example, then is reset for about 25 ps, and so on. Luminous indicator 52 integrates those prolonged conditions l as is illuminated.

If the pulse entering stage S, of register 30 is the pulse F, of the second word of the specific code, different from code SPl, there is then a shift of pulses in register 30, at rate 6, then, up a certain time, pulses F F, and F respectively enter stages S,,.,, 5, and S, of register 30.

Accordingly, gate 37 is off, which permits a new synchronization of the clock, at rate 6, on F according to the already mentioned process. At the same time, gate 44 is turned on, which switches 45 and 46 causing their outputs Q to be turned to condition 1.

If the recognized specific code is a position identification code of mode 1, output Q of 46 remains in condition I up to the occurrence, in 5 (block I), of the pulse F," of the next word, i.e. for about a time t, of 2.5 ms, then is reset for about 50 ,us, and so on. Switch 51 then being in the up position, luminous indicator 52 integrates those prolonged conditions 1 and is illuminated.

In the case of mayday codes, pulses F, F F, and F successively enter stage S, of register 30. Each time a pulse enters stage S,, gate 37 is turned off while 19 is turned on, and a new synchronization is produced already described.

Gate 44 is turned off a second time when pulses F F, and F respectively enter stage S S,.- and S, of register 30.

Gate 44 is turned on a third time when pulses F Ff and F respectively enter the same stages.

Each time gate 44 is on, flip-flop 45 has its condition turned. Flip-flop 46 has its condition turned every other time. On the third oncondition of 44, gate 47 is, in turn, turned on and luminous indicator 48 is operative. The output of 47 remains in condition 1 up to the occurrence, in 5 (block I), of the pulse F, of the next mayday code, i.e. for a time slightly shorter than t, (2.5 ms), then is reset for about 100 1.15, and so on. Luminous indicator 48 integrates those prolonged conditions l and is illuminated.

During mayday code decoding, the outputs Q of flipflops 46 and 50, which control the operation of luminous indicator 52, may have their conditions turned.

Thus, output Q of 46 is turned to level 1 for a time equal to 2(n+2+m) i.e. about 50 1s for each mayday code.

That time duration is too short to enable luminous indicator 52 to light when switch 51 is in the up position.

Similarly, considering flip-flop 50, during each offcondition of gate 37, input S of 50 is turned to level 0 for a time equal to 6. Output Q of 50 is turned to condition 1 and remains in that condition for a time (n+2)6, i.e. up to the offcondition of gate 49, when output Q of 45 is turned to condition 1, under the control of gate 44. The same process is produced twice during mayday code decoding operation. Output O of 50 is turned to level l for a time equal to 2(n-l-2)6, i.e. for about 40 as for each mayday code.

That duration is too short to enable luminous indicator 52 to light when switch 51 is down.

While the principles of the present invention have hereabove been described, in relation with a specific embodiment, it will clearly understood that the said description has only been made by way of example and is not intended to limit the scope of this invention.

What is claimed is:

1. A device for decoding pulse sequences of (11-1) logic conditions each 0 or 1 spaced by one clock period 6, thereby determining 2" normal codes, in which said sequence is marked by an initial pulse F,", and which is arranged to recognize a pulse delayed S6 1 A6 from said F," pulse, where A6 is a time displacement tolerance, comprising the combination of:

a first timing circuit having a time constant 2A6 responsive to said sequence to be triggered by each pulse thereof including, initially, said F," pulse;

a shift register having at least n stages, the input of which is responsive to the 2A6 width pulse output of said first timing circuit;

a clock for generating timing pulses having a period 6 connected to advance said shift register one stage each 6 period, said clock including a pulse generator operating at a frequency (k/6) and a divider-byk circuit responsive to said pulse generator, said divider having an enable input and said K being an integer much greater than (l/2A);

a second timing circuit having a time constant A6, responsive to the output of said first timing circuit;

a third timing circuit having a time constant T, re-

sponsive to the output of said second timing circuit, said third timing circuit being connected to said di vider enable input to synchronize said clock for time T, from pulse F delayed by A6, said T, being a time substantially longer than the longest of said sequence anticipated;

and a decoder coupled to n-l adjacent shift register outputs in parallel, at time (n+l)6 after said F pulse, conditions 0 and 1 along said register outputs representing said word to be decoded.

2. A decoder device according to claim 1, for processing encoded words which comprise, in addition to the (nl logic conditions determining 2" normal codes and the pulse F,, and nth logic condition corresponding to a specific code X and an end pulse F the time interval (n+l )6 from F," to F being determined with tolerance iA6, the said device including; (n+2) stages in said shift register;

a first three-input coincidence circuit which, for a time T following the occurrence of F,", is connected to produce a signal when simultaneously F," and F enter the (n+2)th and 1st stages of said shift register whose outputs are connected to two inputs of the first coincidence circuit, T determined by timing circuit connected to the third input of the said first coincidence circuit, being slightly longer than (n+1 )6 2A6;

a first decoder connected from outputs of ranks 2, 3, (.\'-l (.\'+l (n+1 ofthe shift register for decoding normal codes and a second decoder connected from output of rank x for decoding the specific code X as well a first memory and a second memory wherein outputs of the first decoder and the second decoder are respectively stored under the control of a signal delivered from the first coincidence circuit, and in which said T, is defined as substantially longer than (N-H )6 -l 2A6.

3. A decoder device according to the claim 2, for processing specific codes including, after a word made of n logic conditions within a frame determined by pulses F," and F from one to q words framed by pulse pairs F, and F F, and F F," and F the numbers one to q determining specific codes, time intervals between those frame pulses being equal to (n+1 )6 with a tolerance iA6 and time intervals between F and F,, F and F, being equal to m6 with a tolerance of M6, the said device also comprising;

(n+2+m) stages in said shift register, a second fourinput coincidence circuit connected so that, after a time T from the occurrence of F,", it operates to deliver a signal when pulses F F, and F simultaneously enter the (n+2+m )th, (n+2)th and 1st stages of said shift register whose outputs are connected to the three inputs of a second coincidence circuit, then when pulses including F FF and F and on up to F,"', F,", and F T,,, as determined by a timing circuit connected to the fourth input of the said second coincidence circuit, said last mentioned timing circuit delivering a signal longer than (n+l-l-m) 6+2A6. and said T, being defined as substantially longer than [(n-l-l )(c l-l )+m ]6 2q+l )A6;

a counter, having a capacity (q-l-l connected to be reset by the occurrence of each pulse F,", which counts the number of signals from one to q delivered from the second coincidence circuit;

and means for synchronizing said clock, at rate 6, on each of the pulses F F,, F F F F 4. A decoder device according to claim 3, wherein the means for synchronizing the clock, at rate 6, are characterized by the fact that they comprise:

a reoperable timing circuit, having a time constant 6, which is triggered under the control of the timing circuit having the time constant 2A6;

a set of logic gates connected from said first coincidence circuit output and the outputs of the 1st and (n+2+m)the stages of said shift reigster so as to produce a signal when pulses F F,, F or F, enter the shift register, the said signal being applied to one of the two inputs of a third coincidence circuit whose other input is connected from output of the reoperable timing circuit having a time constant 6;

second timing circuit, having a time constant A6,

which is triggered when the third coincidence cir- 5 cuit is on and having an output connected to said divider-by-k enable input so as to prevent said divider-by-k from operating from a duration A6 following the time 6 defined by the beginning of one of the pulses F F,, F,", entering the shift register.

5. A decoder device according to claim 4, characterized by the fact that:

the timing circuit, having a time constant 6, is constituted by a reoperable monostable circuit having a free-running duration 6;

at least one of the other timing circuits, having a time constant t is constituted by monostable circuits having time constant I,,, said circuits switched as soon as a pulse leading edge is applied to their input and are reset after a time period t,,.

6. A decoder device according to claim 4, for processing secondary radar transponder replies comprising normal codes, including code X, made of n conditions 0 or 1 bracketed by pulses F, and F position identification specific codes formed from a normal code followed by its repetition q'-1 spaced by a standard time interval m6, and of specific mayday codes formed from a normal code followed by q codes of n conditions bracketed by pulse pairs F, and F FF and F F, and F said pulse pairs being time spaced by a standard time interval of M16, the said decoder device comprising:

means connecting the outputs of the counter of capacity (cpl-1 4), where numbers 1 and Cf=3 are indicated, connecting to two independent integrator circuits, which independently decode position identification specific code and mayday specific code, the time constant of the said integrator circuit being long enough so that they are not sensitive to numerous successive markings of duration close to the reply repetition period t 7. A decoder device according to the claim 6, capable of processing specific position identification codes, called SP1 codes constituted by a normal code followed, at a standard interval m6, by a pulse called an SPI pulse, comprising:

a flip-flop whose enable input is connected from the set of logic gates having its erasing input connected from the output of the second coincidence circuit so as to turn its condition when said SPl pulse enters the shift register, and means responsive to said second coincidence circuit to deliver a signal before the end of time T thereby to reset said flipflop;

an integrator, connected from the said flip-flop output, to decode said SPI codes, the said integrator time constant being so long that it is not sensitive to short duration condition changes of flip-flop output, but short enough to be sensitive to numerous successive changes of duration close to the reply repetition period t,.

8. A decoder device according to claim 3, including means which allow the encoded word to be processed only if its pulse F, is applied to the overall device input between times 1', and 7 following reference signal transmission, the said means comprising:

a timing circuit having a time constant 1-,, which is triggered by the reference signal, and a time circuit having a time constant (1 'r,), which is triggered at the end of time 1-,, said circuits being cascade connected; and means connecting the output of said timing circuit having time constant (1- T to a specific enable input triggering said first timing circuit having timing constant A6.

9. A decoder device according to claim 8, wherein said first timing circuit has a time constant A6 and is provided with a specific triggering enable input comprising:

a flip-flop provided with a data input connected from 

1. A device for decoding pulse sequences of (n-1) logic conditions each 0 or 1 spaced by one clock period theta , thereby determining 2n 1 normal codes, in which said sequence is marked by an initial pulse F1o, and which is arranged to recognize a pulse delayed S theta + OR - Delta theta from said F1o pulse, where Delta theta is a time displacement tolerance, comprising the combination of: a first timing circuit having a time constant 2 Delta theta responsive to said sequence to be triggered by each pulse thereof including, initially, said F1o pulse; a shift register having at least n stages, the input of which is responsive to the 2 Delta theta width pulse output of said first timing circuit; a clock for generating timing pulses having a period theta connected to advance said shift register one stage each theta period, said clock including a pulse generator operating at a frequency (k/ theta ) and a divider-by-k circuit responsive to said pulse generator, said divider having an enable input and said K being an integer much greater than (1/2 Delta ); a second timing circuit having a time constant Delta theta , responsive to the output of said first timing circuit; a third timing circuit having a time constant T, responsive to the output of said second timing circuit, said third timing circuit being connected to said divider enable input to synchronize said clock for time T, from pulse F1o delayed by Delta theta , said T, being a time substantially longer than the longest of said sequence anticipated; and a decoder coupled to n-1 adjacent shift register outputs in parallel, at time (n+1) theta after said F1o pulse, conditions 0 and 1 along said register outputs representing said word to be decoded.
 2. A decoder device according to claim 1, for processing encoded words which comprise, in addition to the (n-1) logic conditions determining 2n 1 normal codes and the pulse F1o, and nth logic condition corresponding to a specific code X and an end pulse F2o, the time interval (n+1) theta from F1o to F2o being determined with tolerance + or - Delta theta , the said device including; (n+2) stages in said shift register; a first three-input coincidence circuit which, for a time T2 following the occurrence of F1o, is connected to produce a signal when simultaneously F1o and F2o enter the (n+2)th and 1st stages of said shift register whose outputs are connected to two inputs of the first coincidence circuit, T2, determined by timing circuit connected to the third input of the said first coincidence circuit, being slightly longer than (n+1) theta + 2 Delta theta ; a first decoder connected from outputs of ranks 2, 3, . . . (x-1), (x+1), . . . , (n+1 of the shift register for decoding normal codes and a second decoder connected from output of rank x for decoding the specific code X as well as a first memory and a second memory wherein outputs of the first decoder and the second decoder are respectively stored under the control of a signal delivered from the first coincidence circuit, and in which said T, is defined as substantially longer than (N+1) theta + 2 Delta theta .
 3. A decoder device according to the claim 2, for processing specific codes including, after a word made of n logic conditions within a frame determined by pulses F1o and F2o, from one to q words framed by pulse pairs F11 and F21, F12 and F22, . . . , F1q and F2q the numbers one to q determining specific codes, time intervals between those frame pulses being equal to (n+1) theta with a tolerance + or - Delta theta and time intervals between F2o and F11, F21 and F12, . . . , F2q 1 and F1q being equal to m theta with a tolerance of + or - Delta theta , the said device also comprising; (n+2+m) stages in said shift register, a second four-input coincidence circuit connected so that, after a time T3 from the occurrence of F1o, it operates to deliver a signal when pulses F2o, F11 and F21 simultaneously enter the (n+2+m)th, (n+2)th and 1st stages of said shift register whose outputs are connected to the three inputs of a second coincidence circuit, then when pulses including F21, F12 and F22, and on up to F2q 1, F1q, and F2q, T3, as determined by a timing circuit connected to the fourth input of the said second coincidence circuit, said last mentioned timing circuit delivering a signal longer than (n+1+m) theta + 2 Delta theta , and said T, being defined as substantially longer than ((n+1)(q+1)+mq) theta + (2q+1) Delta theta ; a counter, having a capacity (q+1), connected to be reset by the occurrence of each pulse F1o, which counts the number of signals from one to q delivered from the second coincidence circuit; and means for synchronizing said clock, at rate theta , on each of the pulses F2o, F11, F21, F12, . . . , F2q 1, F1q.
 4. A decoder device according to claim 3, wherein the means for synchronizing the clock, at rate theta , are characterized by the fact that they comprise: a reoperable timing circuit, having a time constant theta , which is triggered under the control of the timing circuit having the time constant 2 Delta theta ; a set of logic gates connected from said first coincidence circuit output and the outputs of the 1st and (n+2+m)the stages of said shift reigster so as to produce a signal when pulses F2o, F11, F21, . . . , or F1q enter the shift register, the said signal being applied to one of the two inputs of a third coincidence circuit whose other input is connected from output of the reoperable timing circuit having a time constant theta ; a second timing circuit, having a time constant Delta theta , which is triggered when the third coincidence circuit is on and having an output connected to said divider-by-k enable input so as to prevent said divider-by-k from operating from a duration Delta theta following the time theta defined by the beginning of one of the pulses F2o, F11, . . . F1q, entering the shift register.
 5. A decoder device according to claim 4, characterized by the fact that: the timing circuit, having a time constant theta , is constituted by a reoperable monostable circuit having a free-running duration theta ; at least one of the other timing circuits, having a time constant to, is constituted by monostable circuits having time constant to, said circuits switched as soon as a pulse leading edge is applied to their input and are reset after a time period to.
 6. A decoder device according to claim 4, for processing secondary radar transponder replies comprising normal codes, including code X, made of n conditions 0 or 1 bracketed by pulses F1o and F2o, position identification specific codes formed from a normal code followed by its repetition q 1 spaced by a standard time interval m theta , and of specific mayday codes formed from a normal code followed by q codes of n conditions bracketed by pulse pairs F11 and F21, F12 and F22, F13 and F23, said pulse pairs being time spaced by a standard time interval of m theta , the said decoder device comprising: means connecting the outputs of the counter of capacity (q+1 4), where numbers q 1 and q 3 are indicated, connecting to two independent integrator circuits, which independently decode position identification specific code and mayday specific code, the time constant of the said integrator circuiT being long enough so that they are not sensitive to numerous successive markings of duration close to the reply repetition period tr.
 7. A decoder device according to the claim 6, capable of processing specific position identification codes, called ''''SPI codes'''' constituted by a normal code followed, at a standard interval m theta , by a pulse called an SPI pulse, comprising: a flip-flop whose enable input is connected from the set of logic gates having its erasing input connected from the output of the second coincidence circuit so as to turn its condition when said SPI pulse enters the shift register, and means responsive to said second coincidence circuit to deliver a signal before the end of time T1, thereby to reset said flip-flop; an integrator, connected from the said flip-flop output, to decode said SPI codes, the said integrator time constant being so long that it is not sensitive to short duration condition changes of flip-flop output, but short enough to be sensitive to numerous successive changes of duration close to the reply repetition period tr.
 8. A decoder device according to claim 3, including means which allow the encoded word to be processed only if its pulse F1o is applied to the overall device input between times Tau 1 and Tau 2 following reference signal transmission, the said means comprising: a timing circuit having a time constant Tau 1, which is triggered by the reference signal, and a time circuit having a time constant ( Tau 2 - Tau 1), which is triggered at the end of time Tau 1, said circuits being cascade connected; and means connecting the output of said timing circuit having time constant ( Tau 2 - Tau 1) to a specific enable input triggering said first timing circuit having timing constant Delta theta .
 9. A decoder device according to claim 8, wherein said first timing circuit has a time constant Delta theta and is provided with a specific triggering enable input comprising: a flip-flop provided with a data input connected from the output of said timing circuit having a time constant ( Tau 2 - Tau 1) and a pulse input connected from the output of said timing circuit having time constant 2 Delta theta ; and a delay circuit, having a delay constant Delta theta , comprising a serially connected resistor and capacitor, said capacitor having one of its electrodes connected to ground and the other connected to the input of the timing circuit having said time constant T1. 